The subject matter relates to semiconductor design technology, and more particularly to a semiconductor memory device including a bit-line sense amplifier to be stably driven even in variation of a production fabrication or a manufacturing process.
Where a low driving voltage is used to implement the power of a memory device, various technical supplements have been used to improve an operation of a sense amplifier in the memory device such as a dynamic random access memory (DRAM). One such supplement is an over-driving scheme of the sense amplifier.
In general, if data of a plurality of memory cells are transferred onto bit-lines, wherein the memory cells are connected to a certain word-line activated by a row address, a bit-line sense amplifier senses and amplifies a voltage difference between two corresponding bit-lines of a bit-line pair.
In the above process, since thousands of bit-line sense amplifiers start to operate simultaneously, a driving time of the bit-line sense amplifiers is determined according to whether or not it is possible to supply a sufficient amount of current for driving the bit-line sense amplifiers.
However, since the operating voltage has been lowered according to a trend of decreased power for the memory device, it is difficult to rapidly supply sufficient current. To solve this problem, an over-driving scheme is adopted so as to supply a voltage higher than a normal voltage, i.e., internal core voltage, onto a power line of the bit-line sense amplifier during an initial operating period of the bit-line sense amplifier (immediately after charge sharing between a cell and a bit-line).
A block diagram and an operation of a conventional semiconductor memory device having an over-driving scheme will be described in detail referring to FIGS. 1 and 2.
FIG. 1 is a circuit diagram of a semiconductor memory device having a conventional over-driving scheme.
As shown, the conventional semiconductor memory device includes a unit memory cell 10, a bit-line sense amplifying unit 20, an equalizing signal generating unit 30, an over-driving unit 40, a first driving power supplying unit NM1, a second driving power supplying unit NM2, a driving power line precharging unit 50 and a data reading path unit 60. The unit memory cell 10 stores a data. The bit-line sense amplifying unit 20 senses and amplifies a voltage difference of a bit-line pair BL and BLB where the data of the memory cell 10 is loaded on. The equalizing signal generating unit 30 generates an equalizing signal BLEQ for precharging the bit-line pair BL and BLB and applies the equalizing signal BLEQ to the bit-line sense amplifying unit 20. The over-driving unit 40 connects an external voltage VDD terminal to a normal voltage supply terminal NODE1 in response to an over-driving pulse OVD. The first driving power supplying unit NM1 supplies a voltage at the normal voltage supply terminal NODE1 to a first driving power line RTO of the bit-line sense amplifying unit 20. The second driving power supplying unit NM2 supplies a ground voltage VSS to a second driving power line SB of the bit-line sense amplifying unit 20. The driving power line precharging unit 50 precharges the first driving power line RTO and the second driving power line SB of the bit-line sense amplifying unit 20. The data reading path unit 60 outputs the data loaded on the bit-line pair BL and BLB to a data pad DQ through transfer lines SIO, SIBO, LIO and LIBO in response to a column-selection signal YI.
The equalizing signal generating unit 30 is embodied by employing a PMOS transistor PM1 and an NMOS transistor NM3 the gates of both transistors receiving a pre-equalizing signal BLEQB and the two transistors connected in series between the external voltage VDD and the ground voltage VSS. The PMOS transistor PM1 receives a source voltage VPP as a substrate voltage and the NMOS transistor NM3 receives a source voltage VBB as a substrate voltage.
FIG. 2 is a timing diagram illustrating signal levels while accessing the semiconductor memory device shown in FIG. 1.
First, if an active command and a low address are input, bit-line splitting signals BISH and BISL are deactivated so that only corresponding unit memory cell array is connected to the bit-line sense amplifying unit 20. Further, as the equalizing signal generating unit 30 deactivates the equalizing signal BLEQ, so as to no longer supply a precharging voltage VBLP to the bit-line pair BL and BLB, an input of data is prepared.
Subsequently, if a corresponding word line WL is activated by the active command, the data of the unit memory cell 10 is loaded on the bit-line pair BL and BLB with a fine voltage difference ΔV.
As first and second enable signals SAP and SAN are activated, the first and second driving power supplying units NM1 and NM2 respectively supply the external voltage VDD and the ground voltage VSS to the first and second driving power lines RTO and SB of the bit-line sense amplifying unit 20. At this time, during a startup driving of the bit-line sense amplifying unit 20, the over-driving unit 40 supplies the external voltage VDD to the normal voltage supply terminal NODE1 in response to an activation of the over-driving pulse OVD so that the first driving power supplying unit NM1 supplies sufficient current to the first driving power line RTO, thereby accomplishing an over-driving. Hereafter, if the over-driving pulse OVD is deactivated, the first driving power supplying unit NM1 drives the first driving power line RTO with a normal voltage VCORE loaded on the normal voltage supply terminal NODE1 because the over-driving unit 40 does not supply the external voltage VDD to the normal voltage supply terminal NODE1. Therefore, the bit-line sense amplifying unit 20 is activated by the first and second driving power lines RTO and SB so as to detect a voltage difference of the bit-line pair BL and BLB and amplify it.
The data loaded on the bit-line pair BL and BLB is output to the data pad DQ through the data reading path unit 60 including the transfer lines SIO, SIOB, LIO and LIOB in response to the column-selection signal YI.
The corresponding word line WL is deactivated based on a precharging command. Because the equalizing signal generating unit 30 activates the equalizing signal BLEQ, the bit-line sense amplifying unit 20 precharges the bit-line pair BL and BLB in response to the activation of the equalizing signal BLEQ. In addition, the driving power line precharging unit 50 precharges the first and second driving power lines RTO and SB of the bit-line sense amplifying unit 20.
Further, as the bit-line splitting signals BISH and BISL are activated, adjacent unit memory cells 10 also share the bit-line sense amplifying unit 20 with each other.
For reference, as described with respect to FIG. 1, a time from activating of the word line WL to activating of the bit-line sense amplifying unit 20 is referred to as a ‘Sensing Margin Delay’. If the sensing margin delay shortens, the bit-line sense amplifying unit 20 reaches an active state such that the fine voltage difference ΔV input to the bit-line pair BL and BLB is not guaranteed after the word line WL is activated. Accordingly, a data error may occur by detecting and amplifying an erroneous data.
As described above, a conventional controlling unit for guaranteeing the sensing margin delay to drive the bit-line sense amplifying unit 20 will be described in detail.
FIG. 3 is a circuit diagram of a conventional bit-line sense amplifier driving controller of the semiconductor memory device shown in FIG. 1.
As shown, the bit-line driving controller includes a signal input unit 70 and a RC delay unit 80. The signal input unit 70 detects an active pulse ACTB_PULSE and a precharging pulse PCGB_PULSE. The RC delay unit 80 adds a sensing margin delay to an output signal of the signal input unit 70 to output a sense amplifier enable signal BLSA_EN.
Herein, the signal input unit 70 activates the output signal to a logic high level in response to the active pulse ACTB_PULSE, and deactivates the output signal to a logic low level in response to the precharging pulse PCGB_PULSE.
Further, the RC delay unit 80 includes an inverter chain for delaying the output signal of the signal input unit 70 to output the sense amplifier enable signal BLSA_EN. A plurality of inverters provided in the inverter chain includes an active resistor and a capacitor at an output terminal of a respective inverter.
Hereinafter, a driving of the bit-line driving controller shown in FIG. 3 will be described briefly.
If the active pulse ACTB_PULSE is activated, the signal input unit 70 activates and outputs its own output signal with a logic high level. The RC delay unit 80 outputs the sense amplifier enable signal BLSA_EN by adding the RC delay according to the active resistors and the capacitors to the output signal of the signal input unit 70.
Thereafter, if the precharging pulse PCGB_PULSE is inputted, the sense amplifier enable signal BLSA_EN is inactivated since the signal input unit 70 inactivates the output signal to a logic low level.
Accordingly, the first and second enable signals SAP and SAN for supplying a driving power voltage of the bit-line sense amplifier are activated in response to the sense amplifier enable signal BLSA_EN.
As described above, the conventional bit-line driving controller enforces the sensing margin delay through the RC delay unit 80. Particularly, the RC delay unit 80 includes the active resistor embodied in an N+ active resistor in consideration of a layout size and process, voltage and temperature (PVT) fluctuation.
However, because the N+ active resistor is affected by variation in a production fabrication or a manufacturing process, it has problem that the resistance value may be fluctuated widely. If a resistance value of the N+ active resistor becomes high, a row to column delay (tRCD) property degrades, but a data error does not occur. However, if the resistance value becomes too low, the sensing margin delay is decreased. Accordingly, before the fine voltage difference ΔV is sufficiently supplied to the bit-line pair BL and BLB, the bit-line sense amplifier may become active so that erroneous data may be detected and amplified.
Therefore, the sensing margin delay may widely fluctuate based on variation in the manufacturing process, and thus, erroneous data from the memory cell may be detected.